October 23, 2014

300mm – 450mm Wafer Issues and Market Trends

300mm – 450mm Wafer Market Trends – Copper – Low-K Convergence: Timing, Trends, Issues, Market Analysis

The semiconductor industry has been increasing the size of wafers about every 10 years. In 2000, semiconductor device manufacturers migrated from 200 mm substrates to 300 mm substrates due to technological advances and manufacturing cost advantages. 300 mm wafers provide more than 2.25 times as many die per wafer, and offer significant economies of scale in the manufacturing process. Approximately 96% of 2012 net orders for wafer fabrication equipment were for 300 mm manufacturing systems. The next planned wafer size increase is expected to be up to 450 mm substrates. 

Increases in wafer sizes have been a natural evolution and manufacturing efficiency improvement for the semiconductor industry for decades, as shown in the figure below.

300mm - 450mm Wafer Issues and Market Trends

 

Throughout its history, the semiconductor industry has migrated to increasingly larger wafer sizes, from one-inch wafers to the 200mm (eight inches) standard predominant today. To gain the economic advantages of a larger surface area, the industry has began using 300mm (12 inches) wafers as the next wafer size. The surface area of a 300mm wafer is more than two times that of a 200mm wafer. 450mm wafers are on the horizon and new hardware will be needed to process 450mm wafers, although some “bridge tools” may come on the market that have dual 450mm-300mm capabilities.

Chipmakers are beginning to shift from using aluminum as the main conducting material for the interconnect circuitry to copper, which has lower resistance than aluminum and can carry more current in a smaller area. Despite the movement to copper interconnects in advanced, multilevel logic devices, most of the world’s advanced integrated circuits are still produced with aluminum/tungsten plug wiring schemes. This will continue to be the case for many years, particularly for memory and embedded memory products.

The interconnect roadmap now accepts that “reduction of the ILD к value is slowing down because of problems with manufacturability. The poor mechanical strength and adhesion properties of lower-к materials are obstructing their incorporation. Delamination and damage during CMP are major problems at early stages of development, but for mass production, the hardness and adhesion properties needed to sustain the stress imposed during assembly and packaging must also be achieved. The difficulties associated with the integration of highly porous ultra-low-κ (к ≤2) materials are becoming clearer…..the slowdown of low-к in this edition, is further reflected by delaying low-к progress by one year in light of the actual pace of deployment of new technologies.”

With CMOS scaling comes reduced sizes and spaces in which to fit interconnects, and the growing problem of increased parasitic resistance and capacitance, which degrades RF performance. Lowering gate-electrode interconnect as an input signal port in analog transistors can fix this. NEC says it has developed a low-k Cu dual-damascene contact interconnect technology, in which the insulating dielectrics are changed from silicon oxide (SiO2) to low-k dielectrics (SiOCH), and the contact metal alternated from high-resistive tungsten (W) to Cu. Burying Cu interconnect with Cu CT plugs in the low-k dielectric material over the CMOS transistor only improved RF performance by 10%, as gate-electrode interconnect resistance could not be reduced sufficiently.

Spin-on dielectrics have the benefit of less dependence on precursors than CVD, that is, one tool can handle a variety of materials, including porogen. Various spin-on low-κ materials including porous materials have been studied. However, PECVD-SiCOH has been the dominant low-κ ILD film. Non-porous spin–on materials have not been used except in some special cases. Spin-on polymer and spin-on MSQ with к ≥ 2.4 are unlikely to be used for actual logic/memory devices, consequently spin-on materials, except porous-MSQ, have been deleted from the potential solutions figure of the ITRS Roadmap.

The roadmap concedes that spin-on-organic ILD has been a total failure. What was the holy grail of chemical companies in the late 1990’s, is at last labeled a dismal failure.

The transition to 300mm fabs resulted in a huge difference in the amount of automation used for processing. There are very high levels of individual tool automation, highly integrated factory CIM systems, large usage of FOUPs and minienvironments, and automated intrabay handling systems

Automation accounts for about 6 percent of the cost of a 450-mm fab, or more than $100 million, double the automation cost burden of a 200-mm production fab.

There are several aspects of copper processing that are challenges. The common barrier layers, Ta/TaN are inert materials and not easy to polish. This has led to a two-step polishing process for removal of the copper first, followed by a second step of removing the barrier layer.

Corrosion of the metal is a problem, as copper shows a high sensitivity to corrosion.

Also, copper can poison other front-end processes, and the copper processing area needs to be isolated from the rest of the fab.

Finally, the complexity of the copper processing leads to challenges in CMP integration. The features on an IC have a variety of densities – highly dense arrays and large bond pads. Each area can polish differently. Also, there are incoming non-uniformities in the copper film, which presents a problem in across-the-wafer CMP uniformity.

The need to minimize total copper loss is critical. Copper loss comes from three areas — field oxide thinning adjacent to a copper interconnect, erosion of copper in arrays with densities up to 90%, and dishing of copper over wide lines of 10 to 100 microns. Minimization of copper loss will keep resistance variations to a minimum. As plating chemistries get more complex and porous low-k materials come on stream, the balance between high throughput and minimal copper loss becomes more critical.

CMP slurry suppliers are working at minimizing thickness variation and copper loss during processing, reducing topography through the entire IC build, and developing process consistency and process stability. Between 1997 and 2000, there was a 500% improvement in planarity by minimizing copper dishing and oxide erosion. Key is a first step slurry with improved planarization performance through engineered particles, proprietary chemicals, and process recipes, and a second step slurry that is highly tuned and highly selective.

A key issue is integration of various components into a single tool for complete deposition and processing of a copper fill. The integrated tool will combine copper fill, copper bevel clean, and copper anneal, all in one clustered tool with a significantly smaller footprint than all individual tools.

For metal barrier and seed, ALD is anticipated to be the means of barrier deposition for future geometries, penetration poses a significant integration challenge. Films created using this approach show excellent resistance to barrier intrusion, even without pore sealing. Because of its high efficiency, UV light or e-beam curing is superior to furnace curing. As the film is cured with UV or e-beam to create the homogeneous nanopores, cross-linking of the silicon oxide matrix also occurs. This improves the film’s hardness and elastic modulus (~1 and 5.8 GPa, respectively, post-treatment).

Strategies vary within the industry, and some companies are pursuing alternatives to low-k materials such as design and packaging effects to reduce capacitance.

Risk and cost management are key factors. Semiconductor manufacturers initially focused their approach on dielectric constant. Now risk and cost are drivers.

Details of the new report, table of contents and ordering information can be found on Electronics.ca Publications’ web site.  View the report450mm/Copper/Low-K Convergence: Timing, Trends, Issues, Market Analysis.

 

 

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