This report discusses the technological and economic impact on the 300mm/Cu/Low-K convergence. This report discusses the timing, trends, issues, and market analysis of 300mm wafers/tools, copper deposition/etch/CMP, and low-k materials.\

TABLE OF CONTENTS

Chapter 1 Introduction        

Chapter 2 Executive Summary        

2.1   Summary of Technical Issues             
2.2   Summary of Market Forecasts             

Chapter 3 300mm Wafer Issues and Trends       

3.1  Introduction                             
3.2  Industry Consortia                        
     3.2.1 International Sematech              
     3.2.2 SEMI                                
     3.2.3 SELETE                              
     3.2.4 J300                               
     3.2.5 SEA                                
     3.2.6 MEDEA                              
3.3 Benefits of 300mm Wafers                  
3.4 Impact on Small IC Manufacturers        
3.5 Impact on ASIC Manufacturers              
3.6 Costs                                      
     3.6.1 Cost Breakdown                      
     3.6.2 Requirements For IC Manufacturers  
3.7 Impact on Automation                       
     3.7.1 Software                           
     3.7.2 Minienvironments                    
     3.7.3 Robots                              
     3.7.4 Cluster Tools                      
3.8 300 mm Fab Construction Plans             
3.9 300mm Prime                               
3.10 450mm Fabs                                
     3.10.1 Overview                           
     3.10.2 450mm Wafer Technical Issues       
     3.10.3 Economic Challenges                

Chapter 4 Copper Issues and Trends                       

4.1  Advantages of Copper                                
4.2  Copper Processing Challenges                        
4.3  Metal Deposition                                     
     4.3.1 Seed Layer                                     
     4.3.2 Bulk Copper Fill                              
4.4 Barriers                                             
4.5 Planarization                                        
4.6 Metrology                                            
4.7 Competing against Aluminum Damascene                 
4.8 Copper for 22nm                                       
     4.8.1 Low-K and Hard Metal Mask Deposition           
     4.8.2 Lithography                                    
     4.8.3 Etch                                           
     4.8.4 Post-etch residue removal                      
     4.8.5 Chemical mechanical polishing                 
4.9 Equipment Suppliers' Copper Electroplating Products  
4.10 Summary                                              
     4.10.1 Advantages/Disadvantages of Cu                
     4.10.2 Processing Issues                             
     4.10.3 Challenges                                   

Chapter 5 Low-K Dielectric Issues and Trends             

5.1   Introduction                                       
5.2   Ideal Dielectric                                   
5.3   Types of Low-K Dielectrics                          
      5.3.1 FSG                                          
      5.3.2 HSQ                                           
      5.3.3 Nanoporous Silica                             
      5.3.4 Spin-on Polymers                              
      5.3.5 BCB                                           
      5.3.6 Flowfill                                      
      5.3.7 CVD                                           
      5.3.8 AF4                                           
      5.3.9 PTFE                                         
5.4   Processing Issues                                   

5.5   Summary                                             
      5.5.1 Integration Issues                            
      5.5.2 Low-K Dielectric Issues                      

Chapter 6 Market Analysis                                

6.1   Semiconductor Market                               
6.2   Road to Recovery                                   
6.3   Market Forecast Assumptions                        
6.4   300mm Wafer Market                                 
6.5   300mm Equipment Market                              
      6.5.1 300mm Equipment Tools                         
      6.5.2 Factory Automation in 300mm Fab Market       
6.6   Copper Processing Equipment Market                 
6.7   Low-K Dielectric Market                             


TABLES

1.1   Planned 300mm Fab Construction                     
3.1   Increase in Wafer Sizes                            
3.2   Cost of 300mm Fab                                  
3.3   300mm Fab Construction Plans                       
3.4   Generic Model For CZ Crystal Yield                 
5.1   Low-K Material Requirements                        
5.2   Low-K Materials                                    
6.1   Worldwide Market Forecast of Si Wafers             
6.2   Worldwide Market Forecast of 300mm Equipment       
6.3   Process Tool Automation For 300mm Fabs             
6.4   Worldwide Forecast of Automation Transfer Tools    
6.5   Worldwide Forecast of Copper Processing Equipment  
6.6   Worldwide Forecast of Low-K Market                 

FIGURES

3.1   Selete's Program Results                           
3.2  Larger Die Sizes More Efficiently Utilize 300mm Wafer Area  
3.3    Increase in IC Size With Time                               
3.4    Economy Of Scale Factor                                     
3.5    300mm and 200mm Fab Cost Comparison                         
3.6    300mm Fabs By Year                                          
3.7    300mm Fabs By Location By Type                              
3.8    Construction Projects 1997-2012                             
3.9    Semiconductor and Equipment Revenues 1994-2010              
3.10   Wafer Thickness Trends With Diameter                        
3.11   Polysilicon Usage By The Solar Industry                     
3.12   Increasing Cost Of Wafer With Time                          
4.1    Reduced Complexity of Copper Interconnect                   
4.2    Interconnect Delay for Copper                               
4.3    ALD Versus PVD Copper Barrier                               
4.4    Copper CMP Steps And Challenges                             
4.5    Electromigration Resistance                                 
4.6    Metal Diffusion Barrier                                     
4.7    Cu Planarization Process                                    
4.8    Copper ECMD Process                                         
4.9    Damascus Complete Copper                                    
4.10   Copper/Low-K Interconnect Schemes                           
4.11   Copper And Low-K Integration Concerns                       
5.1    Low-K Roadmap                                               
6.1    300mm Wafer Market As Percentage of Total Market            
6.2    Electrochemical Deposition Market Shares - Revenues         
6.3    Interconnect Technology Requirements                        
6.4    Copper Implementation By Geographic Region                  
6.5    Copper Implementation By Feature Size                       
6.6    Low-K Deposition Market Shares                              
6.7    Low-K Precursor Market