Look into the future of IC interconnects.  Includes technology trends and options, process materials evolution from 65nm to 22nm, detailed process flows and materials forecasts.  Sections can be ordered as Advanced Dielectrics (all interlevel dielectric applications, highlighting low K materials (CVD, ALD, and Spin on) or Advanced Metallization (interconnect layers of the IC device.  Included are ECD, Electroless, CVD and ALD).

TABLE OF CONTENTS

1 BACKGROUND AND TECHNOLOGY OVERVIEW
1.1 Interconnect Trends
1.2 Factors Driving the Change from Al to Cu wiring
1.3 Interconnect Processes
1.4 Process Flows for Interconnect by IC Product and Generation
1.5 Roadmap Implications
1.6 Process Flows

2 INTERCONNECT PROCESS MATERIAL DESCRIPTIONS
2.1 Poly-Metal Dielectric (PMD)
2.2 Metal Filled Contact Plugs
2.3 Metal for Interconnect Wiring
2.4 Integrated Barrier Seed, PVD
2.5 Copper Cap after CMP
2.6 Inter-Level Dielectric (ILD)

3 INTERCONNECT MATERIALS FORECAST MARKET SIZES
3.1 Poly-Metal Dielectric (PMD)
3.2 Metal Filled Contact Plugs
3.3 Barrier Metal for Copper Wiring
3.4 Metal for Interconnect Wiring
3.5 Copper Cap and Cap Barrier Dielectric
3.6 Inter-Metal Dielectric (IMD), Including Spin-On Low k

LIST OF FIGURES

Figure 1: Percentage of Wafers by Technology with Cu Interconnects
Figure 2: Circuit Delay as a Function of Feature Size
Figure 3: RC Delay, Cu, & Low ?
Figure 4: Al Wire with Oxide Dielectric
Figure 5: Cu Dual Damascene with Oxide Dielectric
Figure 6: Process Sequence for Cu Dual Damascene
Figure 7: Process Sequence for ICs from PMD through W Plug Fill of Contacts
Figure 8: Process Sequence for Al-Cu ICs, All Metal Layers Processed Similarly
Figure 9: Process Sequence for Copper Wiring ICs for First Metal Formation
Figure 10: Process Sequence for Copper ICs for Each Metal Level Beyond M1
Figure 11: Process Sequence Options for Copper Wiring
Figure 12: ?eff Roadmap Delay as Explained in the 2003 ITRS
Figure 13: 65 nm Potential Integration Schemes
Figure 14: Detailed Hybrid Insulator Stack
Figure 15: Drawings of Alternative ILD Stacks
Figure 16: Revenue Forecast for Spin-On Gapfill for PMD (graph and following table)
Figure 17: Spin-On Gapfill for PMD in Volumes (graph and following table)
Figure 18: Revenue Forecast for Only WF6 at 90nm through 32nm
Figure 19: Revenue Forecast for Only TDMAT at 90nm through 32nm nodes
Figure 20: Amount of TDMAT used for CVD Ti of 90nm through 32 nm Nodes
Figure 21: Ta Barrier Sputter Target Revenues
Figure 22: ALD Metal Barrier Forecast
Figure 23: Copper Plating Bath Revenue Projections
Figure 24: Copper Plating Bath Volume Projections
Figure 25: Revenue Opportunity for CoWP or CoWB
Figure 26: Revenue Forecast for CVD Low k Precursors
Figure 27: Volume Forecast for CVD Low k Precursors
Figure 28: Revenue and Volume Forecast for Spin-On Low k Materials
Figure 29: Revenue and Volume Forecast for Spin-On Low k Materials

LIST OF TABLES

Table 1: Materials & Process Options for 2007 (65 nm) & 2010 (45 nm)
Table 2: Properties of Metals
Table 3: 2006 ITRS for MPUs (Near-Term Years)
Table 4: 2006 ITRS for DRAMs (Near-Term Years)
Table 5: 2006 ITRS, Interconnect Difficult Challenges for Advanced Dielectrics
Table 6: Process Flow for MPU and ASIC Products 65 nm to 32 nm Nodes
Table 7: Process Flow for DRAM and Memory Products 65 nm to 32 nm Nodes
Table 8: Process Flow for Flash and NAND Products 65 nm to 32 nm Nodes
Table 9: CVD Precursors by Technology Node from 2005 ITRS
Table 10: Precursors and Their Chemistry
Table 11: Precursors and Their OEMs
Table 12: Revenue Forecast for the amount of 3MS used for Cu Cap