Wafer-level-packages have emerged as the fastest  growing semiconductor packaging  technology with more than 27% CAGR in unit shipments over the next 5 years to come.

Rather than a single solution, wafer-level-packaging technologies are an array of solutions: historically supported by the market growth in flip-chip wafer bumping with electroplated gold, solder bumps and today copper pillars, wafer-level-packages are actually coming in many different flavors, namely Fan-in WLCSP packages, 3D WLP, FO WLP packages, 2.5D Glass / Silicon interposers and  of course 3DIC integration with TSV interconnects.

As this wafer-level-packaging industry develops over time, researchers are observing  that a real infrastructure has emerged by itself  into what is now being called the “Mid-end” of the semiconductor manufacturing environment. Indeed, wafer-level-packages are true “Mid-end” technologies in the sense that they can all be served in the ‘blur zone’ of overlap between the IDMs or CMOS foundries' back-end-of-line (BEOL) wafer fabs and the back-end  wafer bumping assembly facilities of the OSATs and wafer bumping houses.


DETAILED 3DIC & WLP PROCESS FLOWS ANALYSIS

It’s worth noting that there’s a significant difference in how manufacturing is generally performed in the front-end versus in the back-end worlds. The back-end has generally a much greater cost sensitivity but can face scaling issues with time when semiconductor ICs continue to reduce in chip size while increasing in pin-count number. On the other hand, front-end related technologies are more expensive initially but could be preferable because of higher repeatability, yield, throughput and because of better perspectives in the long run when it comes to be able to scale down the technology to smaller pitch dimension while maintaining cost pressure.

For the first time, analysts have been able to gather all the information necessary to benchmark and compare all the different alternatives offered by the present equipment and material tool-box for wafer-level-packaging. All main scenarios are analyzed, including flip-chip wafer bumping trends, Fan-in WLCSP, 3D WLP, FOWLP, 2.5D silicon interposers, 3DIC Via Middle & Via Last process scenarios.

The analysis also include an specific chapter on future trends for PANEL scale packaging such as Embedded die in PCB, FOWLP 2nd generation and poly-silicon or glass sheet interposers based on LCD / PCB / Solar infrastructures.


MARKET FORECASTS FOR 3DIC / WLP EQUIPMENT & MATERIALS

The wafer-level-packaging market shows the greatest potential for significant future growth in the semiconductor industry. It’s a huge business opportunity, especially with the 3DIC technology which is fundamentally changing how processing is done and offers the opportunity for new equipment modifications and new materials development.

Researchers expect the equipment & material market for wafer-level-packaging  to grow significantly in total revenue over the next five years with a CAGR over 60%. The growth will be mainly driven by  the expansion of flip-chip, WLCSP and FOWLP technologies into the wireless mobile industry along with the emergence of 3DIC technology into 3D TSV stacked memories, wide I/O interfaces in logic and memory ICs as well as in CMOS image sensors, MEMS and other heterogeneous 3D stacking applications.

The analysis quantifies the wafer-level-packaging  equipment market evolution for wafer bonders / die pick & place bonders / C2W Bonders / DRIE etching & drilling tools /  CVD / PVD / Plating / Exposure & Lithography / Spray coating / Temporary Bonding & De-Bonding /  Grinding-Thinning-CMP / Wafer-molding / Inspection & Metrology / Test tools.

On the material side, analysts are quantifying the complete wafer-level-packaging materials market evolution for photoresist & coatings  / adhesive tapes / pre-applied & wafer-level underfills / molding compounds / thermal interface materials (TIM) / plating, etching & cleaning chemistries / slurries for CMP / temporary bonding materials / gas  & precursors / sputtering targets / silicon & glass wafer carriers, cap , 2.5D interposer and TGV substrates.


DATABASE with 350+ key equipment & material suppliers for 3DIC / WLP

Researchers can already feel that some consolidation is ahead in the semiconductor equipment and material market. Indeed, because only three players will possibly drive further the 18/14 nm tool market, front-end equipment companies are already anticipating that we are rapidly approaching the end of an era.  One of the first moves was Applied Materials’ acquisition of Semitool last year, enabling the company to expand and sustain in this back-end / WLP direction.

Along with this new research report, analysts will be delivering a 350+  players excel database screening and profiling the detailed activity of small to medium to giant equipment & material suppliers coming either from Front-end, Back-end assembly, PCB, LCD or Solar industries and providing actual solutions for the 3DIC & wafer-level-packaging tool-box.


KEY FEATURES OF THE REPORT

• 2010-2016 wafer forecast for wafer-level-packages with a unique market segmentation of the different flavors  currently blooming in the “Mid-end” of the semiconductor packaging supply chain: namely Flip-chip wafer bumping, WLCSP, FO WLP, 2.5D interposers and 3DICs with TSV interconnects
• Detailed WLP process flows & scenarios analysis putting in evidence which are the critical steps related to each wafer-level-packaging platform and what are the technology alternatives available in the equipment & materials tool-box
• WLP equipment & material market forecasts in unit, volume and revenues from 2010-2016 and based on an unique methodology to estimate realistic sales opportunities in the global ‘Mid-end’ 3DIC & wafer-level-packaging area
• 350+ players DATABASE screening and profiling the detailed activity of small to medium to giant equipment & material suppliers coming either from Front-end / Back-end assembly / PCB / LCD / Solar industry and active in the 3DIC & WLP area

WHO SHOULD BUY THIS REPORT?

Equipment & Material suppliers

• Assess the TAM – total accessible market of your company’s related products in the wafer-level-packaging areas
• Identify technology trends, challenges and precise requirements for each 3DIC / WLP scenarios
• Screen competition activity, identify possible partnerships or targets for M&As in areas close to your current business

R&D organizations & Investors

• Monitor  the global activity and consolidation currently happing in the semiconductor equipment & material business in order to identify new partners, targets and take the right decision before committing to one particular supplier

IDMs, CMOS foundries & OSAT players

• Get an exhaustive list of the 350+ equipment & materials companies supplying solutions in the different  3DIC and wafer-level-packaging areas
• Understand technology trends and benchmark several different 3DIC & WLP scenarios including the future trends for PANEL scale packaging based on LCD / PCB infrastructures

PCB substrate manufacturers

• Get the complete list of semiconductor packaging equipment & materials companies supplying solutions in the blooming 3DIC & wafer-level-packaging area
• Identify technology trends, challenges and issues for each 3D packaging scenario

TABLE OF CONTENTS

Scope of the report & definitions

• Objectives of the report

Executive Summary
 
1)      Budding demand in the “Mid-end”
–  Introduction to WLP platforms and their different flavors
–  2010-2016 WLP wafers forecast
o     Breakdown details in wafer eq. for Flip-chip wafer bumping / WL CSP / FO WLP 1st & 2nd generation / 2.5D Glass & silicon interposers / 3DIC with TSV

2)      3DIC & WLP Equipment & Materials 2010 – 2016 market forecasts
–  Equipment market forecasts (in units and  M$ revenues)  
o  Breakdown details for Wafer Bonders / die bonders / C2W Bonders / DRIE etching & other drilling tools /  CVD / PVD / ECD Plating / Exposure & Lithography / Spray coating / Cleaning / Temporary Bonding & De-Bonding /  Grinding-Thinning-CMP / Wafer-molding / Inspection & Metrology / Test tools
–  Materials market forecasts (in volume shipment and M$ revenues)
o     Breakdown details for Photoresist & coatings  / Adhesive tapes / pre-applied & wafer-level underfills / Molding compounds / Thermal interface materials (TIM) / Plating & cleaning chemistries / Slurries for CMP / Temporary bonding materials/ Gas  & precursors / sputtering targets / silicon & glass wafer carriers, capping, interposers and TGV substrates

3)      3DIC & WLP technologies process flows & manufacturing  trends analysis
–  Focus on Flip-chip wafer bumping  
o  Introduction & background
o     Typical manufacturing process flows
o     Equipment & Materials suppliers involved
o     Key process challenges and issues
–  Focus on WL CSP packaging
–  Focus on FO WLP packaging
–  Focus on Embedded die in PCB  
–  Focus on  2.5D silicon interposers
–  Focus on 3DIC / TSV packaging
–  New manufacturing trends
o     New underfilling techniques (pre-applied, wafer-level underfills, molded underfill, narrow gap 3DIC underfill)
o     PANEL-scale-packaging trends (based on PCB / LCD / Solar infrastructures)
o  Wafer-Scale-Optics manufacturing
o     Glass micro-structuring techniques
 
4)      DATABASE in excel format
–      Detailed analysis of the activity of the  350+ key equipment & material suppliers of the wafer-level-packaging tool-box solutions (activity profiling & key contacts included)
Conclusions & Perspectives   
Appendix