The High K / ALD Precursors report provides information on the applications and markets associated with front end and back end of line precursors used to produce high dielectric constant (K) dielectrics and atomic layer deposition dielectrics and metals.  Market size, growth, and market share statistics are provided.

TABLE OF CONTENTS

REPORT HIGHLIGHTS
Memory Capacitors
Back End of Line
Market Environment

1 INTRODUCTION

2 GATE DIELECTRICS
2.1 Application Description and Current Gate Materials
2.2 FUSI
2.2.1 Advantages of FUSI
2.2.2 FUSI Challenges
2.3 High-? Dielectric and Metal-Gate Technology
2.4 Advantages of Metal Gate (vs. Polysilicon Gate)
2.4.1 Metal-Gate Challenges High-? Metal-Gate Process Flow Notes:
2.5 Future Gate Dielectrics and Requirements
2.6 Material Candidates and Precursors
2.7 Market Timing, Pricing, and Forecast

3 HIGH- CAPACITORS FOR MEMORY DEVICES
3.1 Application Description
3.2 Current Capacitor materials
3.3 Future Dielectric Requirements
3.4 Materials Candidates and Precursors
3.5 Market Timing, Pricing, and Forecast

4 INTERCONNECT
4.1 Interconnect Trends
4.2 ALD Possible Interconnect Technology Applications
4.3 Metal Filled Contact Plugs
4.4 Alternative Interconnect Metals
4.4.1 Chemical Vapor Deposited Aluminum
4.5 Alternative Barrier, Seed, and Capping Metals
4.5.1 Barrier Metals for Copper
4.5.1 Copper Cap after CMP
4.6 Atomic Layer Deposition
4.7 Pricing, Timing, and Forecast

5 PRECURSOR DELIVERY

6 ORGANOMETALLIC PRECURSOR MARKET DYNAMICS
6.1 Supply Value Chain
6.2 Market Shares
6.2.1 Regional Supplier Ranking
6.2.2 Worldwide Market Shares

7 SUPPLIER PROFILES
7.1 Adeka
7.2 Air Liquide
7.3 Air Products & Chemicals (AP)
7.4 SAFC (EpiChem/Sigma Aldrich)
7.5 Dow Chemical (was Rohm and Haas) Electronic Materials
7.6 JSR Corporation and Tri Chemical Laboratories Inc.
7.7 Linde
7.8 Praxair
7.9 UP Chemicals

LIST OF FIGURES

Figure 1: High- and ALD Applications
Figure 2: DRAM Trench Capacitor Application
Figure 3: DRAM Vertical Stacked Capacitor Application
Figure 4: Current MOS Gate Structure
Figure 5: Device with High-? Gate Dielectric
Figure 6: Device with Gate-First
Figure 7: Device with Replacement-Metal Gate-Last
Figure 8: SEM of FUSI Device
Figure 9: FUSI Process Flow
Figure 10: One Possible Metal-Gate-First Process Flow
Figure 11: Intel Penryn’s Replacement-Metal-Gate Process
Figure 12: High- Gate Dielectric & Electrode Precursor Forecast
Figure 13: 70nm Stacked Capacitor
Figure 14: High- Capacitor & Metal Electrode Precursors
Figure 15: Chemical Structure of the Complexes TDMAT and TDEAT
Figure 16: Revenue Forecast for WF6 Only at 90nm through 22nm
Figure 17: Revenue Forecast for TDMAT only at 90nm through 22nm nodes
Figure 18: Revenue Forecast for CVD/ALD Interconnect Metal Barriers, 2 Possible Scenarios
Figure 19: CVD/ALD High- Materials Market for = 90nm, assumes Co as Barrier for = 22nm
Figure 20: CVD/ALD High- Materials Market for = 90nm, assumes Ru is Barrier for = 22nm
Figure 21: 2009 Worldwide Market Share Estimates for High-? Precursors (includes Ti, Ta & Al precursors)

LIST OF TABLES

Table 1: Front End Dielectric Materials & Processes, 2009 & 2012
Table 2: Interconnect Materials & Processes, 2009, 2013 and 2016
Table 3: Gate Related Sections of International Technology Roadmap for Semiconductors
Table 4: Dielectric Materials Capacitance
Table 5: ITRS DRAM Stacked Capacitor Technology Requirements—Near-term
Table 6: 2008 update of the 2007 ITRS for MPU Interconnect Technology Requirements
Table 7: 2008 update of 2007 ITRS DRAM Interconnect Technology Requirements
Table 8: 2007 ITRS, Interconnect Difficult Challenges
Table 9: Materials & Process Options for 2013 (32 nm) & 2016 (22 nm)
Table 10: Organometallic Precursors: Synthesizers and Suppliers to the IC Market