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| IPC Specification Tree |
| Acceptance |
| Assembly |
| Materials |
| Cleaning |
| Process Support |
| Solderability |
| Lead Free |
| Components |
| Optoelectronics |
| Advanced Packaging |
| Cable and Wire |
| EHS/Management |
| Circuit Board Design & Fabrication: |
| Acceptance |
| Fabrication |
| Embedded |
| Design |
| Materials |
| Laminate |
| Interface Design |
| Interfaces |
Media Training: |
| Electronics Assembly |
| Defect and Photo Albums |
| Circuit Board Fabrication |
The Cleanliness and Residue Evaluation Test Board is designed to give the manufacturing process professional a tool to help assess the impact of cleanliness and residues on bare boards and finished assemblies, as well as a tool to assess the impact of changing manufacturing parameters on cleanliness. This artwork package provides .pdf master drawings and Gerber files necessary for fabricating the test board which contains coupons applicable for surface insulation resistance (SIR) testing, ion chromatography (IC), and solder mask adhesion. Released April 2006.
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