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| IPC Specification Tree |
| Acceptance |
| Assembly |
| Materials |
| Cleaning |
| Process Support |
| Solderability |
| Lead Free |
| Components |
| Optoelectronics |
| Advanced Packaging |
| Cable and Wire |
| EHS/Management |
| Circuit Board Design & Fabrication: |
| Acceptance |
| Fabrication |
| Embedded |
| Design |
| Materials |
| Laminate |
| Interface Design |
| Interfaces |
Media Training: |
| Electronics Assembly |
| Defect and Photo Albums |
| Circuit Board Fabrication |
J-STD-075 picks up where J-STD-020 left off by providing test methods to classify worst-case thermal process limitations for electronic components. Classification is referenced to common industry wave and reflow solder profiles including lead-free processing. The classifications represent maximum process sensitivity levels and do not establish rework conditions or recommended processes for an assembler. It outlines a process to classify and label non-semiconductor electronic component’s Process Sensitivity Level (PSL) and Moisture Sensitivity Level (MSL) consistent with the semiconductor industry’s classification levels (J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Devices and J-STD-033, Handling, Packing, Shipping and Use of Moisture/Reflow Sensitive Surface Mount Devices).
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