The 2011 iNEMI Roadmap is the most comprehensive roadmap published to date by the International Electronics Manufacturing Initiative (iNEMI). The complete roadmap report is available here. The document, created by individuals representing all aspects of the electronics manufacturing supply chain, features 27 chapters that provide in-depth discussion of six product sectors and 21 different  manufacturing, component/subsystem, business process and design technologies.

The roadmap identifies major trends in the evolution of Packaging and Component Substrates, with an emphasis on identifying potentially disruptive events (business and technology). It provides the information needed to identify critical technology and infrastructure gaps, prioritize R&D needs to meet those gaps, and initiate activities that address industry needs.

Through its roadmaps, iNEMI charts future opportunities and challenges for the electronics manufacturing industry. These widely utilized roadmaps:

  • Help OEMs, EMS providers and suppliers prioritize investments in R&D
     and technology deployment

  • Influence the focus of university-based research

  • Provide guidance for government investment in emerging technologies

The pace of change in packaging technology today has accelerated to the highest rate in history. This is driven by the penetration of electronics into virtually every segment of society. Communication, transportation, education, agriculture, entertainment, health care, environmental controls (heating and cooling), defense and research all rely heavily upon electronics today. This diversity of application and the never ending demand for both lower cost and higher performance cannot be achieved without major changes in architecture, materials and manufacturing processes. These new technologies include System-in-Package, Wafer Level Packaging, wafer thinning and Through Silicon Vias today. In the near future, we will see additional changes with the incorporation of nano-materials.

The Semiconductor Industry is nearing the end of traditional Moore’s Law scaling and the continued expansion of the industry will depend upon 3D integration to achieve the cost reductions and performance increases that drive the industry. The developments required will be very expensive and the profit stream of the assembly and packaging companies is insufficient. This has already given rise to consolidation in the assembly and packaging industry and a rapidly growing number of consortia to reduce cost through shared research.

The 2011 iNEMI Packaging roadmap is closely coordinated with the Assembly and Packaging Chapter of the International Technology Roadmap for Semiconductors (ITRS).
Today packaging is a limiting factor in both cost and performance for electronic systems. This has stimulated an acceleration of innovation to address these limitations. Design concepts, packaging architectures, materials, manufacturing processes and systems integration technologies are all changing rapidly. This accelerated pace of innovation has resulted in the development of several new technologies and expansion and acceleration of others introduced in prior years. The introduction of new wireless and mixed signal devices, bio-chips, optoelectronics, and MEMS has placed new requirements on packaging.

The electronics industry is nearing the limits of traditional CMOS scaling. The continued growth of the industry, driven by a continuous reduction in cost per function, will require new device types and new package technology. There will be a gap between the time CMOS scaling can no longer maintain progress at the Moore’s Law rate and a new basic switch is ready to replace CMOS.  As traditional Moore’s law scaling becomes more difficult, packaging innovation enabling equivalent scaling through functional diversification and density increase through three dimensional packaging is taking up the slack. A new generation of device / package architectures and electronic material are needed to support the continued increase in functional density and decrease in cost per function expected by the market.

The recent turmoil in the financial markets had a major impact on the market for semiconductor devices. Most reports indicate that the impact resulted in a revenue drop of as much as $25B for 2009. Today a majority of devices are packaged by assembly contractors. These companies operate in very competitive markets with low gross margin. The industry revenue drop reduced their ability to invest in the new technology required to meet emerging market requirements. At the same time the economic conditions generated increased demand for technologies that can reduce the cost per function, particularly in the consumer product sector. The semiconductor market drop in 2009 gave way to record growth in 2010 and slower growth is forecast for 2011.

Technology Challenges
Reliability
There are many factors that determine the reliability of electronic components and systems.  SiP products have higher thermal cycle count due to the use pattern of consumer electronics and greater mechanical stress due to vibrations and dropping for the same reason. The storage and use environments also have a wider range than many conventional electronic systems. Meeting the reliability requirements of future SiP components and systems will require tools and procedures that are not yet available.

Manufacturing Equipment and Processes
The shift in equipment for single chip packaging from dedicated hard tooling based equipment to more flexible manufacturing platforms is still in process.  The drive to higher parallelism in package assembly, higher speed and other changes to reduce cost continues with increased importance in the current economic environment. While this transition is largely complete, the industry is now in the early stages of a move to 450mm wafers. The impact will be greatest in the wafer thinning, saw, die attach, and flip chip placement areas where new equipment is required to handle the larger wafer formats. To support this transition, packaging operations will need to invest in new assembly capability.  
Packaging innovations such as wafer level packaging and system in package have specialized equipment requirements. Current equipment used for wafer level packaging is often modified front end processing equipment. New generations of equipment will be required for wafer level interconnect structures, specialized under bump metallurgy, TSV, and embedded wafer level structures.

Wafer thinning equipment exists today but new equipment will be needed as wafer diameter increases and the die thickness continues to decrease. The principal issues will be stress relief and surface thickness variation including roughness. Wafers thinned to 10 µm or less will require improved processes, such as dry polishing, dry etching, and other process combinations.

Emerging SIP products require assembly equipment with greater versatility and precision. Assembly of SIP with a variety of IC types, optical devices, MEMS devices, and biochips on the same substrate will require substantial extension of current assembly equipment capability.

Materials
There is a broad base of new materials for semiconductor packaging applications driven by the new requirements for improved reliability, performance, cost, and compatibility with new semiconductor materials.
Packaging materials are at the heart of assembly and packaging technology. Packaging material contributes significantly to the packaged device performance, reliability, and workability as well as to the total cost of the package. With the advent of the “More Moore” and “More than Moore” initiatives, the challenges for packaging materials have broadened. Requirements now include traditional packages for future generations devices as well as for new package types such as the SiP package families, wafer level packaging, IPDs, TSVs and for applications in RF, MEMs, and optoelectronics.  
Much of the near-term new materials introduction is driven by environmental regulatory compliance requirements including Pb-Free and RoHS compliance (European Union Directive for Reduction of Hazardous Substances). The migration to “green” materials that are lead-free and halogen-free compatible are in full swing. Materials for the traditional wire bond and flip chip packages including molding compound, die attach materials, underfill materials, thermal interface materials (TIM), and package substrates, will have to be improved to meet lead-free, halogen-free, and low-κ / ultra low-κ requirements.

The development of new packaging technologies, such as SiP, wafer level packaging, embedded die and passives, and TSV, will call for innovations in design of materials and materials processing innovations beyond what is available today. Wafer level packaging will require materials with improved or different properties as it evolves to meet new packaging applications. Different metallization systems for both redistribution traces and under bump metallization, as well as new dielectric polymers, are needed to meet the ever changing reliability requirements for portable electronic devices. The development of fanout WLP and embedded passives/actives will require new low-temperature embedding polymers and low-temperature cure redistribution layer polymers. TSVs will benefit from new dielectric insulators and conductive via filling media for improved low cost manufacturability. Integrated passive devices (IPDs) will also require better materials, with improved electrical properties, for both resistive and capacitive devices.

Warpage
The increasing package diameter, decreasing package thickness, smaller ball size required for the increasing pin count and higher reflow temperatures associated with lead free solder are resulting in warpage becoming the primary limiting factor for ball pitch and ball size in BGA packages. Coplanarity acceptance limits for package terminals (solder balls, pads, leads) are specified for any industry-standard device in the applicable JEDEC, JEITA, IEC, etc., outline drawing.  These coplanarity values, however, are based upon room temperature measurements.

Package Substrates
The package substrates are now the most expensive component in a typical package. This will present an increasing challenge as the thermal density continues to increase and the pitch continues to decrease. The technology exists to meet the requirements but in many cases the cost of the more advanced materials and finer pitch may be prohibitive.

Wafer Level Packaging
Wafer level packaging (WLP) is one of the most rapidly growing packaging technologies. Initially, Wafer Level Packaging (WLP) was defined as a technology in which all of the IC packaging, process steps were performed at wafer level. This definition requires that all package IO terminals are located within the chip outline producing a true chip size package. Today WLP includes packages that are larger than the die with both fan-in and fan-out terminals.  WLP enables decrease in size, increase in operating frequency and cost reduction compared to wire bonding or flip chip. WLPs with fan-in design today are typically for low I/O count and small die sizes. They are mainly being used in portable consumer markets where small size, thickness, and weight are an additional advantage to cost. WLP now incorporates many different structures to meet specific application targets.

MEMS Packaging
MEMs devices are packaged in an unusually wide variety of ways due to the great variation in requirements. These requirements, and the resulting package solutions, go well beyond those of microelectronic packaging and result in an unusual variety of packages.  After several years with only a limited number of applications such as relays, accelerometers and specialized sensors implemented with MEMS technology there is now a rapid rise in the number of designs and types of applications. An expanded array of sensors, fluidics, RF components and other applications are growing rapidly. These new device types require new packaging technology.

Critical Research Needs/Consortia Research Institutes
The packaging roadmap highlights a number of research needs and also provides a summary of major packaging programs underway at various consortia and research institutes.