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High-Density Packaging (MCM, MCP, SIP, 3D-TSV): Market Analysis and Technology Trends

High-Density Packaging (MCM, MCP, SIP, 3D-TSV): Market Analysis and Technology Trends

Information Network, Date of Publication: Nov 7, 2014


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TIN9000

Fifteen billion units shipped in 2015

High-density packaging offer a host of benefits including performance improvements such as shorter interconnect lengths between die, resulting in reduced time of flight, lower power supply inductance, lower capacitance loading, less cross talk and lower off-chip driver power. This report examines and projects the technologies involved, their likely developments, what problems and choices are facing users, and where the opportunities and pitfalls are. The worldwide markets are analyzed and projected.

High-density packages result in a smaller overall package when compared to packaged components performing the same function, hence resulting I/O to the system board is significantly reduced. By sweeping several devices onto one package, board complexity is simplified, thereby by reducing total opportunities for error at the board assembly level.

High-density packages have been subcategorized to better define their content and function.

An MCM is described as a package combining multiple IC's into a single system-level unit. The resulting module is capable of handling an entire function. These MCM packages typically have custom pin out configurations as well.

MCP, or multi-chip packages (sometimes referred to as few chip packages), are typically low lead count combinations of simple IC's. For these packages system control still occurs at the board level. They are primarily produced in volume in standard pin out and package configurations such as DIPs SOJs, QFPs and BGAs.

System-in-Package (SIP) is much more than an IC package containing multiple die. SIP products are fully functional systems or sub-systems in an IC package format. SIP may contain one or more IC chips (wirebonded or flip chip) plus other components that are traditionally found on the system mother board.

The increasing complexity and integration of electronic systems require advanced packaging and multichip module (MCM) techniques.

Various types of multichip packages (MCPs) have been used for many years, but costs have always kept volumes relatively low. Now, however, the felicitous combination of SRAM and flash memory chips in a single package for cell-phone applications is finally creating a high-growth, high-volume market for the multichip packaging.

Multichip packages hold high growth potential, but confusion with MCM technology makes exact forecasting difficult. Regardless of nomenclature, the forecasts offer proof that, by offering high performance in miniaturized spaces, MCPs make an attractive solution for next-generation wireless applications, primarily in mobile phones, but are also likely to become commonplace in various notebook computing applications.

SIP is basically an MCM, but it provides higher density and better time-to-market than the older MCM technology. While MCMs excel in reusability and flexibility, and SoCs excel at performance and density, the SIP is a compromise between the two. Testability and yield are the key deciding factors in the choice between SoC and SIP.

SIP technology is an ideal solution in markets that demand smaller size with increased functionality. However, SIP has the added benefit of compatibility with die design changes and integration of various die technologies (e.g., Si, GaAs, SiGe, SOI, MEMS and Optical) without the high cost and lead time associated with SoC development and manufacturing.

TABLE OF CONTENTS
           
Chapter 1  Introduction    1-1

Chapter 2  Executive Summary    2-1

2.1    Summary of Technology Issues    2-1
2.2    Summary of Market Forecasts    2-7

Chapter 3  Technology Issues and Trends    3-1

3.1    Overview of HDP Technology    3-1
    3.1.1    Need for Multiple IC Integration    3-7
    3.1.2    Challenges of Multiple IC Integration    3-11
3.2    Technical Constraints of Integration    3-12
3.3    Economic Benefits of HDP    3-16
3.4    Technology Issues    3-20
    3.4.1    Substrates    3-22
    3.4.2    Conductors    3-36
    3.4.3    Dielectrics    3-44
    3.4.4    Vias    3-46
    3.4.5    Die Attachment    3-49
    3.4.6    Next Level Interconnection    3-58
    3.4.7    Thermal Management    3-60
    3.4.8    Test and Inspection    3-62
    3.4.9    Design    3-68
3.5    3-D Modules    3-74
3.6    Superconducting Interconnects    3-77
3.7    Known Good Die    3-78
3.8    System In Package (SIP)    3-79
3.9    Multichip Package    3-89
3.10    Package-On-Package (PoP)    3-91

Chapter 4  Applications    4-1

4.1    Overview of HDP Applications    4-1
4.2    Military and Aerospace     4-2
4.3    Computer and Peripheral Equipment    4-8
4.4    Communications    4-10
4.5    Consumer    4-13
4.6    Industrial    4-16

Chapter 5  Competitive Environment    5-1

5.1    Overview of the HDP Competitive Environment    5-1
5.2    Joint Ventures and Cooperative Agreements    5-6
5.3    HDP Manufacturers    5-9
Advanced Packaging Systems    5-10
Aeroflex Laboratories    5-11
AMD            5-12
AMITEC        5-12
Amkor Electronics    5-13
Analog Devices    5-15
Appian Technology    5-16
AT&T        5-16
Ceramic Packaging    5-17
ChipSiP    5-17
C-MAC MicroTechnology    5-17
CNM-IMB        5-18
Conexant        5-18
Control Data        5-19
CTM Electronics    5-19
CTS            5-19
David Sarnoff Research Center    5-20
Delco Electronics    5-21
Digital Equipment    5-21
Elpaq            5-22
Elpida            5-22
ERIM            5-23
Eureka        5-23
Fujitsu        5-24
GEC Plessey        5-25
General Electric    5-25
Hadco            5-27
Honeywell        5-27
Hughes        5-28
Hynx            5-29
Ibiden            5-30
IBM            5-31
ILC Data Device Corp.    5-36
IMEC            5-36
Infineon        5-38
Intel            5-39
Interconnect Systems    5-40
Interconnex        5-41
International Micro Industries    5-41
Integrated System Assemblies    5-42
Intersil        5-43
Kodak        5-43
Kyocera        5-44
Lexmark International    5-45
Lucent Technologies    5-45
MicroModule Systems    5-48
Micron        5-49
Mitsubishi        5-50
Motorola        5-51
nCHIP        5-52
NEC            5-54
NXP Semiconductors    5-54
Pacific Microelectronics     5-55
PMC-Sierra        5-55
Packard-Hughes Interconnect    5-57
Panda Project    5-58
Phillips Laboratory    5-58
Pico Systems    5-59
Quadrant Technology    5-60
Renasas        5-61
RISH            5-61
Rockwell Avionics    5-62
Rogers        5-62
S3            5-63
Samsung Electronics    5-64
Sensonix        5-64
Sharp            5-64
Sheldahl        5-65
Shinko        5-66
Skyworks Solutions    5-67
S-MOS Systems    5-67
Spansion        5-68
Spectra        5-69
Tektronix        5-69
Teledyne Electronic Technologies    5-70
Tessera        5-71
Texas Instruments    5-72
Thomson Consumer Electronics    5-75
Toshiba        5-75
TRW            5-75
United Technologies    5-76
White Electronic Designs    5-76
W.L. Gore & Associates    5-77
Z Systems        5-77


Chapter 6  3-D-TSV Technology    6-1

6.1    Driving Forces In 3D-TSV    6-1
6.2      3-D Package Varieties    6-11
6.3      TSV Processes    6-17
6.4      Critical Processing Technologies    6-19
    6.4.1  Plasma Etch Technology    6-23
    6.4.2  Cu Plating    6-27
    6.4.3  Thin Wafer Bondling    6-28
    6.4.4  Wafer Thinning/CMP    6-32
    6.4.5    Lithography    6-33
6.5  Applications    6-36
6.6  Limitations Of 3-DPackaging Technology    6-42
    6.6.1  Thermal Management    6-42
    6.6.2 Cost    6-44
    6.6.3     Design Complexity     6-45
    6.6.4      Time To Delivery     6-50
6.7  Company Profiles    6-51
ASE            6-51
ALLVIA        6-51
Amkor        6-52
BeSang        6-55
Chartered Semiconductor    6-57
Cubic Wafer    6-58
Elpida Memory    6-58
Freescale    6-59
Fujikura    6-59
IBM        6-60
Infineon    6-61
Intel        6-62
Jazz Semiconductor    6-63
Micron Technology    6-64
NEC        6-66
NXP        6-67
Oki Electric    6-69
Renesas    6-70
Samsung    6-71
Sharp        6-73
Silex Microsystems     6-74
STATS ChipPAC    6-75
STMicroelectronics    6-76
Tessera    6-77
Tezzaron    6-79
Toshiba    6-82
TSMC    6-83
UTAC    6-84
Ziptronix    6-85
ZyCube    6-87

Chapter 7  Market Forecast    7-1

7.1    Overview of Multichip Modules    7-1
7.2    Driving Forces    7-5
7.3      Alternative Packaging Technologies    7-7
7.4    Worldwide IC Market Forecast    7-24
7.5    Worldwide Packaging Market Forecast    7-26
7.6    Worldwide MCM Market Forecast    7-28
    7.6.1    Worldwide Forecast By Substrate Type    7-33
    7.6.2    Worldwide 3-D Through Silicon Via (TSV) Market    7-37
    7.6.2    Market Forecast By Application    7-48
    7.6.3    Market Forecast By End Use    7-54
7.7    Wafer Level Packaging    7-60


LIST OF TABLES

3.1     Multichip Modules Vs. Circuit Board Assemblies    3-17
3.2      MCM Cost Comparison    3-19
3.3      Substrate Technology Features    3-25
3.4      Metal Conductors in MCMs    3-37
3.5      Comparison of Thin-Film and Thick-Film Technologies    3-40
3.6      Characteristics of Dielectric Materials    3-47
3.7     CTE of Common Substrates and Adhesives    3-56
3.8     Comparison of MCM Testers    3-67
3.9     Density Comparisons of Single Package and 3-D MCM    3-75
5.1     MCM Manufacturers    5-10
6.1    3-D Mass Memory Volume Comparison Between Other Technologies and TI’s 3D Technology In Cm3/Gbit
6.2    3-D Mass Memory Weight Comparison Between Other Technologies and TI’s 3D Technology In Grams3/Gbit
6.3    Institutions Working In The Area Of 3D TSV    6-16
6.4    Companies Working In The Area OF 3D TSV    6-17
7.1      Worldwide IC Package Market Forecast    7-27
7.2      Worldwide MCM Market     7-36
7.3      Worldwide MCM-C Market By Application    7-50
7.4      Worldwide MCM-D Market By Application    7-51
7.5      Worldwide MCM-L (MCM, SiP, MCP) Market By Application    7-52
7.6      Worldwide MCM Market By Application    7-53
7.7    WLP Demand By Device     7-62
7.8    WLP Demand By Device     7-63


LIST OF FIGURES

1.1     Schematic Cross-Section View Of An MCM-D     1-3
1.2     Cross-Section Of The RF And Microwave MCM-D Structure    1-5
1.3     Thin Film Layers On The Planarized Core Layer Of MCM-SL/D Technology    1-8
1.4     Flip Chip MCP    1-11
1.5     SIP Cross Section    1-14
3.1    IC Packaging Trends    3-2
3.2     Technology Tree For HDP Types    3-3
3.3     Form Factor Decrease By Package Type    3-10
3.4     High Power Package Technology Roadmap    3-34
3.5     Comparison Between Wire Bonding And Bump    3-51
6.1    3-D Through-Silicon Via (TSV)    6-3
6.2    Silicon Efficiency Comparison Between 3D Packaging Technology And Other Conventional Packaging Technologies
6.3    Comparison Between 2D And 3D Packaging Interms Of The Accessability And Useablity Of Interconnection
6.4    3D Packages    6-10
6.5    Through-Silicon Via (TSV)    6-18
6.6    Moore's Law For Active Element Density    6-25
7.1    Comparison Of SOC, MCM, SIP, And SOP    7-8
7.2     Materials Integrated In The SOP Concept     7-11
7.3    Digital, RF And Optical Function Integration In One SOP Package    7-12
7.4    Substrate Warpage Control     7-14
7.5    Effect Of Elastic Modulus On Sop Package Substrate Warpage    7-15
7.6     Area Assembly Pitch Reduction     7-17
7.7    Summary Of Package/Board Materials With Modulus And CTE     7-18
7.8      Low Loss Dielectrics And Future Requirements     7-20
7.9     Eye Opening Measurements For Low Loss Dielectrics At 5 Gbps Data Rate     7-22
7.10    Projection of 3-D TSV Applications And Process Requirement    7-39
7.11    Market Forecast of 3-D TSV Wafers    7-40
7.12    Worldwide Market Of End Use Applications    7-59

 

Nov 7, 2014
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