Cost and Investment Implications of 3D NAND

Cost and Investment Implications of 3D NAND

Forward Insights, Date of Publication: May 7, 2014, 112 Pages
US$25,000.00
FI5840

The NAND flash industry is on the cusp of a technology inflection point.  2D NAND is reaching its scaling limits with 3D NAND its anointed successor.

In the 2D NAND era, the underlying process technology (with a few exceptions) is essentially the same amongst all the NAND flash manufacturers.

However, in the 3D NAND era, all the NAND flash manufacturers are developing different 3D NAND concepts with variations in the process implementation. The different processes will impact the investment and manufacturing cost for each of the 3D NAND technologies.

This report provides a detailed analysis of the fab and manufacturing implications of 3D floating gate and charge trap NAND concepts from Samsung, Toshiba, SK Hynix and Intel-Micron versus 16nm 2D NAND.  The analysis is based on a bottoms-up process flow analysis for each 3D NAND technology and 16nm 2D NAND.  

Some of the questions addressed in this report include:

- What are the main drivers of the process complexity for 2D NAND and 3D NAND?
- What is the tool commonality between 3D NAND and 2D NAND?
- What is the cost impact of moving the CMOS under the array in 3D NAND?
- How much does it cost to build a Greenfield 3D NAND fab and how does it compare to a 2D NAND fab?  What is the equipment footprint required and the breakdown of the investment by process modules?
- What is the front end manufacturing cost of a 3D NAND wafer compared to a 2D NAND wafer?
- What is the investment required to convert an existing 2D NAND fab to 3D NAND?  What is the impact on the fab cycle time and manufacturing capacity?
- What is the incremental investment required to transition a 32 layer 3D NAND fab to 64 layers?  What is the impact on fab cycle time and manufacturing capacity?

TABLE OF CONTENTS

CONTENTS III

LIST OF FIGURES    V

LIST OF TABLES  IX

EXECUTIVE SUMMARY 1

INTRODUCTION 3

THE PATH TO 3D   4
   NAND Flash Technology Evolution  4
   3D NAND Flash Memory Cell    6
       Implementation of Floating Gate Cells into 3D NAND Flash Arrays 6
       Floating Gate Memory Cell Scaling Challenges 8
       Charge Trapping Memory Cell Development and Remaining Reliability Issues    17
       Optimization of Charge Trapping Memory Cell for the Application in 3D Arrays    20
2D AND 3D NAND PROCESS FLOW   25
  Technology Overview and Process Challenges    25
3D CONCEPTS  34
  Overview  34
   CMOS formation  35
       Conventional CMOS Adjacent to Memory Array  35
       CMOS Placement Below Memory Array    37
   3D Memory Array Formation  39
       Toshiba p-BiCS  39
       Samsung TCAT  48
       3D Floating Gate    56
   BEOL for 3D Concepts  61
   Fundamental Limitation in 3D NAND Fabrication   63

2D AND 3D NAND PROCESS COMPARISON    64
  Process Complexity Comparison  64

COST AND INVESTMENT IMPLICATIONS OF 3D NAND    75
  Greenfield Fab    75
       Fab Investment    75
       Equipment Footprint    80
       Wafer RPT and Cycle Time 82
       Wafer Costs    84
       Sensitivity Analysis  86
   Converting from 2D NAND to 3D NAND   88
       Wafer Capacity  88
       Investment/De-investment  89
   3D NAND Technology Migration    96
       Wafer Capacity  96
       Investment/De-investment  96
       Wafer RPT and Cycle Time 101
       Wafer Costs    103

CONCLUSION  105

ABOUT THE AUTHORS  109
  Services    111
   Contact  112


List of Figures

Figure 1   NAND Flash Technology Evolution [2], [3]  5
Figure 2   NAND Flash Memory Coupling Ratio, other coupling components, and Cross-talk [2], [3]  7
Figure 3   Reduced gate coupling ratio and increased programming voltages for scaled FG NAND dimensions (a) due to increased FG-FG capacitances [2], [7]    8
Figure 4   Electrons Stored on the Floating Gate [2]  9
Figure 5   Bit line pitch scaling limitation issue in (a) and (b), and resulting FG trimming (c) [2], [4]  10
Figure 6   20 nm FG NAND Flash Technology (a) and Sandisk/Toshiba FG NAND shrink roadmap (b), which all show reduced shrinking of the cell dimension in word line direction (bit line pitch or cell Y direction) except for the IMFT 20 nm planar FG cell [5] , [6]  11
Figure 7   Simulated Random Telegraph Noise Amplitude Distributions for scaled Floating Gate Technology Nodes [7], [8]  12
Figure 8   Random telegraph noise and the effect of high WL-WL electrical fields [7]  12
Figure 9   Gate Coupling Ratio Variation by Different Poly Plug Depth and Program Saturation [9]  14
Figure 10   Program and Erase Behavior of Fully Planar FG Capacitors and Field Conditions for Different FG Options [10]  15
Figure 11   Details of the Micron 20 nm planar FG NAND cell ((a) and (b)) and its program and erase characteristics (c) [11], [12]    16
Figure 12   Tunneling current characteristic for direct tunnelling with different oxide thicknesses and Fowler-Nordheim-Tunneling [13]   18
Figure 13   Erase characteristics of a charge trap memory device with various metal gates offering workfunctions comparable to n+-poly until p+-poly silicon as well as values in-between   [14]  18
Figure 14   Tradeoff between retention and erase performance for charge trap stacks with different stoichiometry of the SiN charge storage layer (a), a more effective high-k top oxide (b) or a blocking oxide to avoid the charge loss through the blocking oxide (c)   [2], [15], [16], [17]    20
Figure 15   Cross-sectional view of a SONOS gate all-around structure [2]  21
Figure 16   Illustration of the improvement in the field distribution of the SONOS structure by the enhanced coupling due to the gate all-around structure [2]  22
Figure 17   Comparison of the program and erase performance of a planar SONOS stack memory cell and cell with a gate all-around structure taking advantage of the improved coupling ratio [18]    22
Figure 18   Comparison of the retention loss for planar and surround gate SONOS structures [18]  23
Figure 19   Performance improvement of program and erase due to the scaling of the Si-pillar diameter enhancing the gate coupling of the charge trap layer [19]  23
Figure 20   Details of Micron 20 nm planar FG NAND Flash Technology [12], [20]    25
Figure 21   Gate oxide formation in array, LV and HV periphery      26
Figure 22   Deposition of the thin floating gate poly-Si and IGD stack in cell array and periphery      26
Figure 23   Process steps of the SADP sequence for 20nm half pitch STI patterning  27
Figure 24   Process status after STI etch and fill and after opening of the periphery and select gate contacts    28
Figure 25   Process steps of the SAQP sequence for 16 nm NAND word line patterning    29
Figure 26   An additive litho adds the select and periphery transistors   The gate etch is a common process step in cell array and periphery      30
Figure 27   The contacts to the gates (CG) and contacts to diffusion are etched and filled      31
Figure 28   The staggered bit line contacts are etched and filled which again requires a SADP process      32
Figure 29   Overview of the 3D NAND concept chapter and the 3D construction kit  34
Figure 30   CMOS fabrication ­ STI finalization  35
Figure 31   CMOS part - contact oxide deposition and polish after the implant steps and silicidation35
Figure 32   CMOS finalization ­ contact polish  36
Figure 33   M0 formation right on top of the CMOS devices in case of CMOS below array    37
Figure 34   CMOS below array with two finalized metal layer    37
Figure 35   CMOS below array ­ final stage with transition contacts to connect the logic and artificial bulk to either use as connection layer (TCAT/3D-FG) or pipe formation layer (p-BiCS)    38
Figure 36   Overview of the initial proposal of the BiCS concept [21]    39
Figure 37   Structure of the p-BiCS concept [21]  40
Figure 38   Formation of the pipe structure to connect two associated memory cell chains    41
Figure 39   Vertical etch of the channel holes to later place the charge trap stack and the memory string channel  41
Figure 40   Formation of charge trap stack and channel with Macaroni structure and core filler[19]    42
Figure 41   Separation of control gates by vertical cut etch and subsequent fill with sacrificial nitride  42
Figure 42   Select gate channel formation by hole etch stopping on memory string channel poly  43
Figure 43   Separation of select gate planes by cut etch and removal of the memory cut etch sacrificial fill to allow silicidation of all gate planes  44
Figure 44   a) Initial etch step to form the stair case gate connection structure, b) structure after one resist trim and cycle with two levels formed into the oxide, the periphery is etched accordingly to open the space for contacts to the CMOS part  44
Figure 45   Finalization of the stair case etch by deposition of a nitride etch stop layer and oxide fill of the deep remaining trenches    45
Figure 46   Contact formation to the stair case to provide electrical connection to the gate planes and CMOS part    46
Figure 47   Intermediate structure with contacts to control gates, select gates and first metal layer M0 on top  47
Figure 48   Schematic overview of the fundamental structure of the TCAT concept [23]    48
Figure 49   Schematic overview of the fundamental structure of the TCAT concept used in our proposal and the Samsung reference for V-NAND [24]    49
Figure 50   Structure after poly layer removal in the array area and multilayer stack deposition    50
Figure 51   TCAT structure after channel hole formation and channel deposition with core filler    50
Figure 52   TCAT - staircase formation status after 2nd etch cycle­ 1st etch+1st strip+ 2nd etch  51
Figure 53   TCAT structure after staircase etch finalization and oxide fill  51
Figure 54   Intermediate structure with contacts to control gates, select gates and first metal layer M0 on top  52
Figure 55   Intermediate TCAT structure with polished staircase fill oxide, etch gate cut and removed sacrificial nitride, the charge trap stack is already done with oxidized channel poly as tunnel oxide and deposited nitride and top oxide 52
Figure 56   Finalization of the memory cells by deposition of the gate stack and recess etch, the electrical connection of the lower end of the string is solved by a junction implant through the gate cut creating a rectangular channel select device    53
Figure 57   The 3D structure after the sourceline implant and subsequent silizidation to reduce the resistance, finally the gate cut is filled with oxide and polished    54
Figure 58   The tungsten gate planes and the CMOS devices are contacted in the staircase structure by contacts with a huge height difference    54
Figure 59   TCAT structure after M0 formation, the channel holes are separately contacted within the M0 processing    55
Figure 60   Comparison of the charge trap layer arrangement in (a) BiCS and (b) TCAT [25] and (c) SMArT [13]    55
Figure 61   a) Overview of the proposed 3D floating gate approach, showing 4 FG cells per string and the respective select devices, b) publication by SK Hynix and their proposal for a 3D FG structure with extended sidewall control gate ­ESCG [26]  56
Figure 62   Initial state of the 3D floating gate NAND fabrication after the multilayer deposition, etched channel holes and FG cavity formation by anisotropic wet nitride recess etch    57
Figure 63   Vert   FG structure with finalized floating gates by poly deposition and wet etch for separation, subsequently the tunneling oxide is formed by thermal oxidation and the channel is formed by poly and core filler deposition    58
Figure 64   Vert   FG structure after staircase formation and subsequent oxide deposition to fill the resulting trenches  58
Figure 65   Vert   FG structure after sacrificial nitride removal to open the cavities for ILD deposition and control gate formation  59
Figure 66   Vert   FG structure with finalized control gates and IPD after metal deposition and subsequent wet recess for gate separation   59
Figure 67   Vert   FG structure with fabricated contacts to control gate planes and CMOS devices, furthermore sourceline silicidation is depicted by the purple circles  60
Figure 68   Vert   FG structure with formed connections to realize reliable upper select devices 60
Figure 69   Vert   FG structure after M0 formation which includes the connection to the vertical pipe channels on top of the contacts    60
Figure 70   BEOL stack after M1 polish including the finalized M1 and C1 on top of M0  61
Figure 71   BEOL stack after M2 oxide polish including the finalized M2 and C2 on top of M1  61
Figure 72   Final BEOL stack after Polyimid deposition and opening showing the used nomenclature in our process proposals    62
Figure 73   Final sequence of memory device gate fabrication in the 3D NAND approaches with recess etch, gate deposition and final wet etch gate separation, the formulas show the link between thickness of the horizontal layer and the gate cut dimension 63
Figure 74   Overview of the key contributors for 16nm NAND process complexity compared to 3D NAND    65
Figure 75   Process Complexity Drivers ­ 32L 3D NAND  66
Figure 76   Number of process steps by process group ­ 32L 3D NAND  67
Figure 77   Process Complexity Drivers ­ 64L 3D NAND  68
Figure 78   Number of process steps by process group ­ 64L 3D NAND      69
Figure 79   Lithography Layers by Technology    70
Figure 80   Main Thin Film Layers by Technology  71
Figure 81   Main Etch Layers by Technology   72
Figure 82   Main Clean Layers by Technology   73
Figure 83   3D NAND Tool Commonality with 2D NAND    74
Figure 84   Fab Investment by Technology  76
Figure 85   Number of Equipment  77
Figure 86   Equipment Investment Breakdown by Technology    77
Figure 87   Equipment Investment Breakdown by Process Module    78
Figure 88   Equipment Investment Breakdown by Process Module    78
Figure 89   Fab Investment by Tool Class  79
Figure 90   Equipment Footprint for 100kwpm Capacity    81
Figure 91   Equipment Footprint Breakdown by Process Module for 100k wpm Capacity    81
Figure 92   Wafer Raw Processing Time Breakdown by Process Module    82
Figure 93   Wafer Processing Cycle Time by Technology    83
Figure 94   Front End Wafer Cost by Technology  85
Figure 95   Front End Wafer Cost Breakdown    85
Figure 96   Fab Investment Sensitivity Analysis  87
Figure 97   Equipment Footprint Breakdown for Given Area by Process Module for 32 Layer 3D NAND    88
Figure 98   Impact on Wafer Capacity of Conversion from 2D NAND to 3D NAND    89
Figure 99   Invest/De-invest for Conversion from 2D NAND to 3D NAND    90
Figure 100   Incremental Invest by Technology for Conversion from 2D NAND to 3D NAND  91
Figure 101   % Increase in Incremental Invest by Technology for Conversion from 2D NAND to 3D NAND    91
Figure 102   % Increase in No   of Tools by Technology for Conversion from 2D NAND to 3D NAND    92
Figure 103   De-invest by Technology for Conversion from 2D NAND to 3D NAND    93
Figure 104   % Decrease in No   of Tools (De-invest) by Technology for Conversion from 2D NAND to 3D NAND  93
Figure 105   % Decrease in De-invest by Technology for Conversion from 2D NAND to 3D NAND94
Figure 106   Impact on Wafer Capacity of Conversion from 32L to 64L 3D NAND  96
Figure 107   Investment/De-investment for Conversion from 32L to 64L 3D NAND    97
Figure 108   Incremental Investment by Technology for Conversion from 32L to 64L 3D NAND  98
Figure 109   % Increase in Incremental Investment by Technology for Conversion from 32L to 64L 3D NAND    98
Figure 110   % Increase in No   of Tools by Technology for Conversion from 32L to 64L 3D NAND99
Figure 111   De-invest by Technology for Conversion from 32L to 64L 3D NAND  99
Figure 112   Wafer Raw Processing Time Breakdown by Process Module    101
Figure 113   Wafer Processing Cycle Time by Technology    102
Figure 114   Front End Wafer Cost by Technology  103
Figure 115   Front End Wafer Cost Breakdown    104

List of Tables

Table 1      Comparison of the characteristic electrical parameters of p-BiCS and TCAT  24
Table 2      Comparison of the process complexity for 193 nm immersion litho vs   SADP and SAQP 33
Table 3      TCAT vs  SMArT - Key Process Steps Comparison  56
Table 4      Fab Investment    80
Table 5      Equipment Footprint incl   support for 100k wpm Capacity  82
Table 6      Raw Processing Time/Cycle Time    84
Table 7      Front End Wafer Cost ­ 32L 3D NAND    86
Table 8      Sensitivity Analysis ­ Total Fab Invest per 100k wpm    87
Table 9      Conversion Costs from 100k wpm 16nm 2D NAND Fab    95
Table 10    Conversion Costs for 32 Layer to 64 Layer Migration  100
Table 11    Raw Processing Time/Cycle Time    102
Table 12    Front End Wafer Cost ­ 64L 3D NAND    104
 



Date of Publication:
May 7, 2014
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