The Assembly and Test Cost and Price model covers wafer sorts, assembly of leadframe and organic substrates packages including EMIB, wafer level packaging and InFO and class test. The model is user customizable and we are continually adding new features.
The IC Cost and Price Model allows users to easily estimate the cost and price of most low power silicon-based ICs such as SOCs, microprocessors, ASICs, DRAM, NAND and more. The IC Model is very easy to use, the user only has to make eight selections or entry's and there is help for many of them. The model then presents a detailed analysis of cost and pricing and offers over seventy options for customization. Cost includes wafer fabrication, wafer test, packaging and final test.
Strategic Cost and Price Model - a forward looking model that projects Logic processes out to 13.5nm, DRAM and 2D NAND out to 1z plus 3D NAND and 3D XPoint. The model covers the top 3 DRAM, Foundry,and NAND manufacturers and leading logic manufacturers by node and produces detailed process flows, equipment requirements, materials requirements and wafer cost projections. The model is fully pre populated but also customizable customizable for process, equipment and materials. The model is wafer cost only and does not include packaging or test.
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