Test Assembly and Packaging

Date of Publication: Jul 18, 2017

This report offers a complete analysis of the Process Control market, segmented as: Lithography Metrology; Wafer Inspection/Defect Review; Thin Film Metrology; and Other Process Control Systems. Each of these sectors is further segmented. Market shares of competitors for all segment is presented.

Date of Publication: Jul 18, 2017
This report discusses the packaging trends for higher performance and density driving advanced packaging technology solutions for mobile and IoT applications. One of the key enabling technologies to achieve these goals is thin 3D-packaging with integration. Developments have lately been made with various embedding technologies, such as eWLB/Fan out WLP and embedded devices. Higher integration levels and lower profiles are also achieved with wafer-level processes, at which most R&D is concentrated in the commercialization of 2.5D IC´s (with silicon interposer) & 3D ICs, as well as coreless substrate. Furthermore, there is tremendous pressure to decrease overall package height even with the additional dies stacking through innovation in wafer thinning, TSV, and ultrathin interconnects.

Date of Publication: Jul 18, 2017
TSV is a vertical electrical connection that passes completely through a silicon wafer or chip to create 3D ICs or packages. The drivers for market adoption of 3D ICs are increased performance, reduced form factor and cost reduction.  This report analyzes the market for TSV ICs, equipment, and materials. A critical element in enabling 3D integration is the Through-Silicon Via (TSV); a large, metal-filled conduit passing through the silicon substrate. TSV provides the high-bandwidth interconnection between stacked chips.

Date of Publication: Mar 29, 2016
This report analyzes the worldwide markets for Semiconductor Automated Test Equipment (ATE) in terms of spending (US$) for the following Application Areas: Consumer Electronics, Telecom & IT, and Others. The global market for Semiconductor Automated Test Equipment (ATE) is projected to reach US$3.16 billion by 2022, driven by the "digitalize or die" challenge faced by industries and the ensuing significance of semiconductors. Surviving the digital disruption is the compelling new reality for industries across the globe. The Internet, Web 2.0, robotics, artificial intelligence, Internet of Things, and big data analytics are changing the flavor of modern industries. Digital transformation of industries and companies is inevitable in the emerging digital economy. The imminent mass adoption of digital technologies will amplify the commercial opportunity in semiconductor manufacturing as the computational muscle required to power the digital age will be provided by the semiconductor industry. Taiwan represents the largest and the fastest growing independent regional market worldwide with annual spending on semiconductor ATE waxing at a CAGR of 3.3% over the analysis period. Growth in the market is primarily led by huge electronics and semiconductor manufacturing industry established in the country over the years.

Date of Publication: Apr 1, 2016
The flip chip technology market is expected to grow from USD 19.01 Billion in 2015 to USD 31.27 Billion by 2022, at a CAGR of 7.1% between 2016 and 2022. The report aims at estimating the size and future growth potential of the flip chip technology market across different segments on the basis of bumping process, packaging technology, packaging type, product, application, and region. Consumer electronics application is expected to be the fastest-growing segment in the flip chip technology market during the forecast period, followed by automotive application.

Date of Publication: Jun 17, 2014
Driven by the development of mobile devices, the worldwide IC packaging and testing industry saw a significant growth in 2014. With leadership in technology and production capacity, the Taiwanese IC packaging and testing industry has enjoyed the highest growth in the world. As the availability of wearable devices and the IoT (Internet of Things) increases, new opportunities and challenges await the Taiwanese IC packaging and testing industry. This report recaps the recent development of the worldwide and Taiwanese IC packaging and testing industry while forecasting their developments in 2015 and beyond from the aspects of market trends and industrial structure.

Date of Publication: Jul 25, 2015
Three-Dimensional (3D) Through-Silicon-Via (TSV) technology is steadily gaining importance as a highly-advanced semiconductor packaging model that dramatically improves chip performance and functionality. 3D TSV devices possess stacked silicon wafers interconnected vertically by employing TSVs. The 3D TSV devices offer numerous benefits in wafer/chip assembly, which include superior performance as compared to conventional techniques, reduction in package size, heterogeneous integration, and superior performance. Driven by the growing demand for innovative, high-performance chip architectures featuring benefits such as superior performance, power consumption and form factor features, 3D TSV technology is making robust progress in the semiconductor industry.