Test Assembly and Packaging

US$4,500.00
Date of Publication: Jul 25, 2015
Three-Dimensional (3D) Through-Silicon-Via (TSV) technology is steadily gaining importance as a highly-advanced semiconductor packaging model that dramatically improves chip performance and functionality. 3D TSV devices possess stacked silicon wafers interconnected vertically by employing TSVs. The 3D TSV devices offer numerous benefits in wafer/chip assembly, which include superior performance as compared to conventional techniques, reduction in package size, heterogeneous integration, and superior performance. Driven by the growing demand for innovative, high-performance chip architectures featuring benefits such as superior performance, power consumption and form factor features, 3D TSV technology is making robust progress in the semiconductor industry.