Wafer Fabrication Costs Model and Equipment Requirements

Strategic Cost Model

IC Knowledge, Date of Publication: Mar 26, 2015

The IC Knowledge - Strategic Cost Model covers the top three producers of DRAM, Foundry logic, IDM logic and NAND (2D and 3D) out to 5nm for logic and 12nm for memory. The model provides detailed projections of cost, materials and equipment sets. The model is packed with both historical actual data and forward projections. This is the tool of choice for OEMs and Materials companies trying to understand the impact of future technologies on their business. Anyone purchasing the model gets twelve months of updates with reasonable phone and email support.

Specifically the model covers: DRAM - Samsung, Micron and SK Hynix, Foundry - TSMC, Global Foundries, Samsung, IDM Logic - Intel MPU, IBM Internal processor, ST Micro, NAND - Samsung, Toshiba, SK Hynix 2D and Samsung and Toshiba 3D.
In each case we present a detailed introduction date, general process's details, process flows in order, pitch by layer and node, mask layers, multi patterning usage and total masks. Process blocks, pitch and multi patterning can be edited for each case.
For each target company and process every 300mm fab they have is predefined so that if you juts pick a fab the fab details and supported processes are pre defined (although you can override them) and detailed outputs of equipment and materials requirements are provided.

Supported processes
The Model supports DRAM out to 1x nm, Foundry and IDM logic out to 5nm and NAND in 2D out to 1z as well as 3D.

Supported wafer sizes
300mm and 450mm

Supported cost elements
Wafer cost only..

Who should buy this product

The IC Knowledge - Strategic Cost Model - is in use at many large IDMs, Consortia, Materials companies and OEMS forward projecting markets and costs as the industry implements the ITRS and 450mm,.

Recent revisions
Revision 1402 - first full release of the new company and node based version of the Strategic Model. Additions since the last Beta are: Fixed an error where the 40nm - SS - NAND - 3D - 24L process wasn't available in the process selection drop down list. Fixed an error in the 130nm ST Micro process metal pitches. Deleted the STMicro - 20nm - FDSOI process. Updated SOI starting wafer costs. Fixed an error in the Litho upgrade calculation. Fixed an error in the cost per block calculation. Added Samsung Xian 3D NAND Fab. Fixed an error in the 3D NAND Channel Connect block. Fixed an error in the aSi throughput. Fixed errors in the RCAT and SRCAT process blocks. Adjusted TSMC starting wafer types and fixed a bug in the wafer type drop down. Fixed errors in the length of building and building systems depreciation lengths. Eliminated Global Foundries 20nm process. Added SK Hynix M11 fab and changed M12 to NAND. Added SK Hynix - NAND - 2D. Added locations to Fab data. Adjusted the TSMC 28nm and 20nm processes and pitches. Adjusted pitches for Global Foundries, IBM and Samsung. Adjusted the Intel 22nm, 14nm and 10nm flows. Updated NF3 useage. Added NH3 to TiN and TaN deps. Added damascene cobalt via process and applied to Intel 10nm and smaller processes for critical layers. Added CVD - Co deposition and Co CMP processes and materials. Added H6B2 to critical W deps. Adjusted DRAM pitches and multipatterning usage. Updated 2D NAND pitches and multi patterning usage. Updated TSMC 10nm pitches and added 16FF+. Added custom blocks to the NAND process blocks drop downs. Added HDPILD to the 3D NAND blocks drop downs. Expanded custom blocks to 40 rows each. Added support for 450mm wafers. Fix an error that caused the NAND sheet NGL litho option drop downs to not porperly populate. Added TSV as a block option on all product sheets. Added Toshiba - NAND - 3D. Updated DRAM processes to add oxide prior to contact. Added new Toshiba Fab6? for 3D NAND. Added ALD, CMP, CVD, Dry Etch and PVD user defined steps. Fixed a CMP step in the Saddle Fin proces sthat should have been CMP - W buy was CMP - poly. Adjusted how equipment counts are calculated. Added a data flow block diagram.
Revision 1403 - Fixed an issue with the TSMC 10nm process missing a default wafer size. Fixed an issue with missing processes in the 'Main Selection' process dropdowns. Adjusted TEOS usage. Adjusted HBR usage. Implemented a new capital equipment calculation methodology that improves accuracy. Changed Intel 14nm and smaller nodes to 13 metal layers based on an analysis of Intel's 14nm part. Added an 'Investment Summary' sheet. Adjusted bulk gas usage.
System Requirements
The Model runs inside of Microsoft Excel and requires the user to have Excel 2010 installed on their computer. The are are known compatibility issues with Excel 2007 and Open Office and any third party Excel compatible product.
Model Cost and How to Buy
A single user license allows one user on one computer and is $5,000, an enterprise license allowing an unlimited number of users at a company is $12,000. The model is delivered by email within a few hours of our receiving an order. The model cost includes twelve months of updates plus twelve months of reasonable levels of phone and email support. A Web Ex training session is available on request. Renewal costs at the end of twelve months are discounted 1/3 off the current prices.

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Date of Publication:
Mar 26, 2015
File Format:
Excel File via E-mail
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