A number of technical and operational trends within the semiconductor manufacturing industry are strengthening the need for more effective advanced equipment solutions. These trends include: Development of Smaller Semiconductor Features. The development of smaller features, now as small as 20nm in production and 10nm in R&D, enables semiconductor manufacturers to produce larger numbers of circuits per wafer and to achieve higher circuit performance. Transition to 3D device structures. Foundries are adopting 3D FinFET transistors starting at 14/16 nm technology nodes to get improved performance and use less power in 1x technology nodes. Memory makers will move to 3D NAND and vertical structures for next generation NAND technology. Transition to 3D Integration Technology. Three-dimensional (3D) integration of active devices, directly connecting multiple IC chips, offers many benefits, including power efficiency, performance enhancements, significant product miniaturization, and cost reduction.
The Strategic Cost and Price Model - 2019 is now available with eight new fabs, expanded logic and DRAM process coverage, updated data and many other enhancements. Specifically the model covers: DRAM - Samsung, Micron and SK Hynix, Foundry - TSMC, Global Foundries, Samsung, IDM Logic - Intel MPU and ST Micro, NAND - Samsung, Toshiba, and Intel-Micron and 2D and 3D NAND, 3D XPoint for Intel-Micron.
The Assembly and Test Cost and Price model covers wafer sorts, assembly of leadframe and organic substrates packages including EMIB, wafer level packaging and InFO and class test. The model is user customizable and we are continually adding new features.
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