This report analyzes the wearable industry and markets for the two wearable camps described above. Forecasts are also presented for semiconductor content and markets for MEMs devices, sensors, CPUs and low-power MPUs, GPS, and connectivity chips.
A number of technical and operational trends within the semiconductor manufacturing industry are strengthening the need for more effective advanced equipment solutions. These trends include: Development of Smaller Semiconductor Features. The development of smaller features, now as small as 20nm in production and 10nm in R&D, enables semiconductor manufacturers to produce larger numbers of circuits per wafer and to achieve higher circuit performance. Transition to 3D device structures. Foundries are adopting 3D FinFET transistors starting at 14/16 nm technology nodes to get improved performance and use less power in 1x technology nodes. Memory makers will move to 3D NAND and vertical structures for next generation NAND technology. Transition to 3D Integration Technology. Three-dimensional (3D) integration of active devices, directly connecting multiple IC chips, offers many benefits, including power efficiency, performance enhancements, significant product miniaturization, and cost reduction.
The Assembly and Test Cost and Price model covers wafer sorts, assembly of leadframe and organic substrates packages including EMIB, wafer level packaging and InFO and class test. The model is user customizable and we are continually adding new features.
The IC Cost and Price Model allows users to easily estimate the cost and price of most low power silicon-based ICs such as SOCs, microprocessors, ASICs, DRAM, NAND and more. The IC Model is very easy to use, the user only has to make eight selections or entry's and there is help for many of them. The model then presents a detailed analysis of cost and pricing and offers over seventy options for customization. Cost includes wafer fabrication, wafer test, packaging and final test.
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